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Memory and bus architecture
RM0008
Note:
Note:
2.4
1
2
3
4
5
These options should be used in accordance with the Flash memory access time. The wait
states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:
zero wait state, if 0 < SYSCLK ? 24 MHz
one wait state, if 24 MHz < SYSCLK ? 48 MHz
two wait states, if 48 MHz < SYSCLK ? 72 MHz
Half cycle configuration is not available in combination with a prescaler on the AHB. The
system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.
The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB
clock.
The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz. The
prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.
Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing the Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
For further information on Flash memory operations and register configurations, please refer
to the STM32F10xxx Flash programming manual.
Boot configuration
In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Table 6 .
Table 6.
Boot modes
Boot mode selection pins
Boot mode
Aliasing
BOOT1
BOOT0
48/995
x
0
1
0
1
1
Main Flash memory
System memory
Embedded SRAM
Doc ID 13902 Rev 9
Main Flash memory is selected as boot space
System memory is selected as boot space
Embedded SRAM is selected as boot space
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